--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   11:50:13 04/08/2011
-- Design Name:   
-- Module Name:   /home/goofy/Pulpit/UCiSW_projekt/adc_test_bench.vhd
-- Project Name:  WAVE_Recorder
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ADC
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY ADC_test_bench IS
END ADC_test_bench;
 
ARCHITECTURE behavior OF ADC_test_bench IS 
 
   -- Component Declaration for the Unit Under Test (UUT) 
   COMPONENT ADC
   PORT(
         CLOCK : IN  std_logic;
			GAIN_ENABLE : IN  std_logic;
			GAIN : IN std_logic_vector (7 downto 0);
			CHANNELS_SAMPLE_ENABLE : IN  std_logic;
			SPI_MISO : IN  std_logic;
			CHANNEL_A_SAMPLE : OUT std_logic_vector (15 downto 0);
			CHANNEL_B_SAMPLE : OUT std_logic_vector (15 downto 0);
			AMP_CS : OUT std_logic;
			AMP_SHDN : OUT std_logic;
         SPI_SCK : OUT  std_logic;
			SPI_MOSI : OUT std_logic;
			AD_CONV : OUT std_logic;
			BUSY : OUT std_logic;
			SPI_SS_B : out STD_LOGIC;
			SF_CE0 : out STD_LOGIC;
			DAC_CS : out STD_LOGIC;
			FPGA_INIT_B : out STD_LOGIC);
   END COMPONENT;    

   --Inputs
   signal CLOCK : std_logic := '0';
	signal GAIN_ENABLE : std_logic := '0';
	signal GAIN : std_logic_vector (7 downto 0) := X"00";
	signal CHANNELS_SAMPLE_ENABLE : std_logic := '0';
	signal SPI_MISO : std_logic := 'X';

 	--Outputs
	signal CHANNEL_A_SAMPLE : std_logic_vector (15 downto 0);
	signal CHANNEL_B_SAMPLE : std_logic_vector (15 downto 0);
	signal AMP_CS : std_logic;
	signal AMP_SHDN : std_logic;
	signal AD_CONV : std_logic;
   signal SPI_SCK : std_logic;
	signal SPI_MOSI : std_logic;
	signal BUSY : std_logic;
	signal SPI_SS_B : STD_LOGIC;
	signal SF_CE0 : STD_LOGIC;
	signal DAC_CS : STD_LOGIC;
	signal FPGA_INIT_B : STD_LOGIC;
 
BEGIN 
	-- Instantiate the Unit Under Test (UUT)
   uut: ADC PORT MAP (
          CLOCK => CLOCK,
			 GAIN_ENABLE => GAIN_ENABLE,
			 GAIN => GAIN,
			 SPI_MISO => SPI_MISO,
			 CHANNELS_SAMPLE_ENABLE => CHANNELS_SAMPLE_ENABLE,
			 CHANNEL_A_SAMPLE => CHANNEL_A_SAMPLE,
			 CHANNEL_B_SAMPLE => CHANNEL_B_SAMPLE,
			 AMP_CS => AMP_CS,
			 AMP_SHDN => AMP_SHDN,
			 AD_CONV => AD_CONV,
          SPI_SCK => SPI_SCK, 
			 SPI_MOSI => SPI_MOSI,
			 BUSY => BUSY,
			 SPI_SS_B => SPI_SS_B,
			 SF_CE0 => SF_CE0,
			 DAC_CS => DAC_CS,
			 FPGA_INIT_B => FPGA_INIT_B
   );
 
	CLOCK <= not CLOCK after 20 ns;
	
	GAIN <= "00010001";   

	process
	begin
		loop
			wait until BUSY = '0';	
			
			CHANNELS_SAMPLE_ENABLE <= '0';
					
			GAIN_ENABLE <= '1';
			wait for 40 ns;
			GAIN_ENABLE <= '0';
			
			wait until BUSY = '0';	
			
			CHANNELS_SAMPLE_ENABLE <= '1';
			wait for 40 ns;
			CHANNELS_SAMPLE_ENABLE <= '0';
		end loop;
	end process;
	
	process
		type DummyDataType is array (33 downto 0) of STD_LOGIC;
		variable DummyData : DummyDataType := 
			( 'U', 'U',
			  -- bit: 0, 1, ... 13
			  '1', '1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1',
			  'U', 'U',
			  -- bit: 0, 1, ... 13
			  '0', '1', '0', '0', '0', '0', '0', '0', '0', '0', '1', '0', '1', '1',
			  'U', 'U' );
	begin
		wait until AD_CONV = '1';
		
		for i in DummyData'RANGE loop
			wait until rising_edge (SPI_SCK);
		
			SPI_MISO <= DummyData(i);
		end loop;
	end process;
END;
